Pre Silicon

Architect, implement, productize testability needs through the entire IC design cycle

Design For Test (DFT)

Increasing design complexity calls for scalable and optimized DFT solutions that address the need for high test quality with low test cost, while minimizing design area and timing closure impact. We have extensive experience in architecting and implementing DFT for ICs in varying market segments. We will engage seamlessly with your design, verification and timing closure teams as well as test and product engineering teams to provide a world-class solution that meets all your needs.

  • Innovate Promptly with High Quality

    Design complexity demands innovation to achieve quality and cost goals

  • Engagement Spectrum

    Value add R&D partner to add capacity for seamless execution

  • Scalability

    Global presence to enhance scalability

Key Expertise Areas

DFT at RTL Level

Generating or modifying RTL to create DFT friendly designs. A few examples are test access, memory BIST and repair, and scan clocking

DFT at Gate Level

Experienced in industry standard tools to create custom flows and tools that provide the best DFT results in the design. Examples: DFT integration into synthesis, scan insertion, memory BIST, JTAG, Boundary scan, core test, verification, IR-analysis, sdc constraints, GLS with timing

Pattern Generation

Understanding the knobs to be turned to get the results of industry standard ATPG tools. Production and debug pattern generation and handoff for all tests, fault simulation, low power patterns

Post-silicon support

Strong test and instrumentation experience augments and accelerates the test bring-up. Test bring-up, debug, test pattern robustness, fault diagnosis, repair solutions, yield enhancement


  • Automotive

    The rise in the use of semiconductors in automotive has resulted in a need for increased quality measured in DPPBs. In addition, functional safety requirements are driving the adoption of techniques such as logic BIST. Our prior work in the automotive domain makes us a valuable partner in implementing effective quality conscious solutions.

    • Digital DFT Architecture
    • Quality
    • Coverage
    • BIST for FuSa

  • Artificial Intelligence

    Artificial intelligence has been moving towards custom silicon for both training and inference. This has led to IC's with massive transistor counts and high-speed interfaces, to enable the massively parallel computation required by these tasks. Anora has in-depth experience in DFT and ATE test for these "Big-D" chips.

    • Architecture for complex AI semiconductor designs
    • Scalability
    • Memory Repair

  • Industrial

    Industrial chipsets demand high reliability and quality. DFT architects and test architects at Anora work together to devise methodologies and processes to ensure highly qualified and reliable products through sound DFT architecture and implementation

    • Quality
    • Reliability
    • Cost

  • Consumer

    Mobile and wearable technologies require special attention to power domain considerations as well as power during testing. Test cost optimization also remains a care-about. We can analyze your requirements and devise a DFT solution tailored to your needs

    • Low power
    • Clocking architectures
    • DFT for test cost optimization


Coming Soon